1. Field of the Invention
The present invention relates to electrically programmable read only memory (EPROM) devices and, in particular, to a contactless flash EPROM cell array structure that includes polysilicon isolation blocks, and a process for its fabrication.
2. Description of the Related Art
An electrically programmable read only memory (EPROM) device is a non-volatile memory integrated circuit which is used to store binary data. Power can be removed from an EPROM without loss of data. That is, upon reapplying power, the originally stored binary data are retained.
In addition to its data retention capability, an EPROM can also be programmed to store new binary data. Reprogramming is accomplished by first exposing the EPROM to an ultraviolet (UV) light source in order to erase the old binary data. A UV-transparent lid on the packaged EPROM chip allows this erasure to occur. Following erasure, the new binary data are written into the EPROM by deactivating the chip select line in order to switch the EPROM's data outputs to inputs. The EPROM address inputs are then set to a starting value, the desired data are connected to the data inputs and the data are written into the data storage register identified by the address inputs. The address inputs are then incremented and the cycle is repeated for each storage register in the EPROM array.
In an EPROM read operation, the binary data stored in the data storage register identified at the address inputs are connected to the chip's data output buffers. If the EPROM's chip select signal is activated, then the binary data from the selected storage register are provided to the databus.
An electrically erasable programmable read only memory (EEPROM) device is a variation of the EPROM design wherein binary data are read, written and erased electrically. A single operation erases a selected data storage register. In the so-called "flash" EPROM device, all data storage registers in the memory array are electrically erased in a single operation.
A standard T-shaped flash EPROM cell array 10 is illustrated in FIGS. 1-3. The T-shaped EPROM cell array 10 includes a thin oxide 12 overlying P-type silicon substrate 14 between N+ drain regions 16 and N+ graded source regions 18, both of which are formed in P-type silicon substrate 14. A polysilicon (poly 1) floating gate 20 overlies thin oxide 12 and field oxide 22. Overlying poly 1 floating gate 20 is a layer of interpoly insulator 24, typically a composite layer of oxide-nitride-oxide (ONO). A polysilicon (poly 2) control gate 26 overlies insulating material 24. Metal bit line 28 is connected to N+ drain regions 16 by drain contacts 30. As shown in FIGS. 1 and 3, one drain contact 30 is shared by two EPROM cells of the array.
A conventional "contactless" flash EPROM cell is illustrated in FIGS. 4-8. As shown in FIG. 4, an EPROM cell within the array 40 does not share one contact between two cells, as is the case in the conventional flash EPROM cell. Rather, in a contactless flash EPROM, the N+ bit lines are contacted every 32, 48 or 64 cells.
As shown in FIGS. 4-6, and further described in U.S. Pat. No. 5,371,030 to Bergemont which is fully incorporated herein by reference, two adjacent cells within array 40 share the same graded source line S and are separated from other cells in the array along the same polysilicon (poly 2) word line 42 (not shown in FIG. 5) by field oxide (FOX) isolation strips 44. That is, as is best shown in FIG. 5, the separate drains D.sub.1 and D.sub.2 of adjacent cells share a common source S. Each column of shared-source cells is separated from adjacent shared-source cells (e.g. D.sub.1 '/D.sub.2 '-S' is separated from D.sub.1 /D.sub.2 -S and D.sub.1 "/D.sub.2 "-S" in FIG. 5) along the same poly 2 word line 42 by FOX isolation strips 44.
As further illustrated in FIGS. 4, 6 and 7, conventional contactless flash EPROM cell array 40 includes a polysilicon (poly 1) floating gate 46, interpoly insulator 48 (typically an ONO composite layer) and array field oxide regions 50.
Traditionally, increases in EPROM, EEPROM, flash EPROM and contactless flash EPROM cell array density have been accomplished by reducing the dimensions of the cell features produced by the photolithographic and etching procedures utilized in fabricating the cells. Unfortunately, conventional FOX fabrication processes, e.g. Local Oxidation of Silicon (LOCOS), result in FOX isolation strips that are wider, due to the lateral encroachment of oxide during the thermal LOCOS growth process, than the minimum geometry that can be produced by lithographic and etching processes.
Still needed in the art is a contactless flash EPROM cell array with isolation structures of the minimum geometry and processes for their fabrication.